Performance of EEPROMs are considered by many to be a substantial improvement over EPROMs (erasable programmable read-only memories). While EPROMs require an ultraviolet light source to erase stored information, EEPROMs can be erased with electric signals. Not only is electrical erasure faster, but it allows a single byte of information to be erased whereas ultraviolet light will erase all information stored in an EPROM memory device. One drawback to using EEPROMs is that cell size of an EEPROM is considerably larger, due to the fact that an EEPROM cell has two transistors while an EPROM has only one. Thus in applications in which circuit density is extremely important, a EEPROM may not be as desirable as an EPROM.
A type of memory device, called a flash EEPROM, has been developed which provides electrical erasing capability and has a circuit density comparable to an EPROM. Structurally, a flash EEPROM is most often similar to an EPROM, although several different structures have been demonstrated. Functionally, a flash EEPROM can be programmed by hot electron injection, like an EPROM, and is erased via Fowler-Nordheim tunneling, as an EEPROM. However, a disadvantage which exists with a flash EEPROM that does not exist with either conventional EPROMs or EEPROMs is a programming time delay due to over-erasure. In a flash EEPROM, erasing is accomplished by applying a bias to a source so that electrons stored in a floating gate tunnel to the source region. However in doing so, the floating gate often becomes positively charged, thereby lowering the threshold voltage (V.sub.T) of the channel region. Lower V.sub.T values correspond to weak hot electron generation, thus time involved in programming a memory cell is increased. Typically in programming a flash EEPROM cell, a control gate and a drain region are brought to a relatively high voltage, thereby creating an electric field at a junction of the channel region and drain and generating hot electrons at the junction. These electrons are then injected into the floating gate, thereby charging, or programming, the cell. If V.sub.T is low, the electric field which is created is weak, and electron generation at the junction is reduced. Thus, a lower V.sub.T implies a longer programming time.
A few solutions to programming delays are known; however, the solutions typically have other problems which make implementation undesirable. For example, one solution is to dope the channel region more heavily. While a higher doping concentration prevents V.sub.T from becoming too low during an erase operation, a highly doped channel region will have fewer mobile carriers, and thus will have a lower read current. Low read currents are undesirable because more time is required to sense whether or not the channel region is "ON" or "OFF", in other words to read the logic state of the memory cell. Another solution to programming delays is to avoid over-erasing the memory cell, or to avoid lowering the threshold voltage. This can be accomplished by a series of "partial erasures" and sensing after each erasure whether or not the cell has been erased. A problem with a series of erasures is that the time necessary to erase a cell is significantly increased, and is therefore unfavorable. Yet another solution to programming delays, which will be described in more detail at a later point, is to apply a series of pulse programming voltages to the control gate of the cell. While pulsing the programming voltage enhances electron injection into the floating gate of the cell, several pulses are required, thus programming time is increased.
Therefore, a need exists for an improved nonvolatile memory device, and more specifically for a nonvolatile memory device which is electrically erasable, which has dense circuitry, and which has improved programming speed over conventional, erasable nonvolatile memories.